FIG. 1 illustrates a conventional Phase Locked Loop (PLL) clock signal generation circuit 100 of the prior art. A PLL 105 used to generate a clock signal 106 from an input clock reference signal 107. A similar clock signal generation circuit 100 without PFD (110) is also sometimes described as a Frequency Locked Loop (FLL).
A PLL is typically used in digital system to provide a clock signal having a frequency programmed at the operating frequency of the digital system, as shown in FIG. 1. The PLL circuit includes a Phase Frequency Detector (PFD) 110, charge pump 115, loop filter 120, voltage controlled oscillator 125, and a divider 130.
A conventional PLL/FLL generates clock signals having a frequency that is a fixed multiple of an input reference clock frequency. The output clock frequency (Fout) is determined by following formula:Fout=Fin×N. 
A problem with a conventional PLL/FLL clock generation circuit is that a fixed output clock frequency is not efficient for a digital system with significant power supply noise. In particular, the power supply voltage can droop and overshoot when the digital system switches on and off. This is because the system impedance includes a die capacitance and a packaging inductance. Typically the system impedance has 1st and 2nd order droops, where the 1st order droop occurs at a much higher range of frequencies than the 2nd order droops.
For many digital circuits, the maximum clock frequency is denoted as Fmax, which is the maximum clock frequency (at a given supply voltage) for pipeline circuits to operate properly. If the supply voltage droops too much because of switching activity, then critical paths will incur timing failure. Thus the output clock frequency is selected based on the lowest voltage that is anticipated in view of voltage droops. Another way to understand this issue is that there has to be a sufficient nominal voltage margin to handle Vdd droops. However, if the voltage margin is raised too high, then the power consumption increases and power is wasted.
Attempts have been made to reduce the performance penalty associated with supply droops. For the Intel 1A Nehalem family of processors the power supply impedance profile has a 1st and 2nd order droop regions, where the 1st order droop occurs at a much higher frequency than the 2nd order droop region. The Intel 1A Nehalem family of multi-core processors adapts the output frequency of the PLL primarily in response to the high frequency 1st order supply droops using adaptive analog frequency/supply tracking. As illustrated in FIG. 2, the Nehalem approach includes a resistively coupled analog tracking loop to adjust a linear voltage regulator of the PLL. Details of the Nehalem approach are discussed in U.S. Pat. No. 7,042,259 and in the paper, “Next Generation Intel Micro-architecture (Nehalem) Clocking Architecture,” by Kurd et al, 2008 Symposium on VLSI Circuits Digest of Papers, pp. 62-63. Note that the Nehalem approach, which is based on adapting to the fast 1st order droop, attempts to stay locked with an average fixed ratio of average frequency.
Therefore, in view of these deficiencies, a new approach to generating clock signals is desired.